1. Field of the Invention
The present invention generally relates to a communication interface which guarantees the coherency of data transferred between a communication bus and a host interfaced thereto.
2. Description of the Prior Art
Historically, an important goal of communication interfaces has been to ensure the integrity of data transfers between a communication bus and a host. This is particularly important, and can be more difficult to achieve, in systems having a large number of high speed bus devices communicating with a host. As a result, various interface buffering schemes have been developed to ensure data integrity.
Such an interface is disclosed in U.S. Pat. No. 4,623,997, issued to Tulpule on Nov. 18, 1986, entitled COHERENT INTERFACE WITH WRAPAROUND RECEIVE AND TRANSMIT MEMORIES. The disclosed interface is designed to ensure the coherency of messages transferred between an asynchronous bus and an attached subsystem. As disclosed in that patent, a coherent message is one in which the data or parameters refer to a unique computation performed in a unique data set and also belonging to a unique time frame. Incoherency occurs when a message contains data belonging to different time frames, computations or data sets. This typically occurs when data from a previous message is overwritten before it can be processed by a host CPU.
According to that patent, data integrity or coherency is achieved through the use of separate, wraparound receive and transmit memories for storing message strings. As messages are received by the interface, they are sequentially stored in the next available address in a wraparound receive buffer. Once the last memory address in the receive buffer has been written to, the next data segment is written into the first buffer location, wrapping around and overwriting any old data stored there. A similar arrangement is disclosed for the transmission of messages from the host CPU to a bus device.
Although the invention disclosed in the above mentioned patent is more likely to maintain data coherency than predecessor designs which featured, for example, a single buffer for both receive and transmit message strings, it does have certain limitations which may adversely affect data integrity and coherency. For example, it relies on sizing the receive memory so that sufficient receive messages can be stored to avoid overwriting messages which have not yet been processed by the host CPU. Sizing of the receive memory can only be done after certain assumptions are made about the number of devices which will be sending messages to the host CPU along with the estimated message length and transmission frequency. Although a safety factor can be built into this calculation, there is no guarantee that data coherency can be maintained. Systemic changes in either the frequency or length of messages sent from the bus devices, or in the host CPU's processing capability could result in unprocessed messages being overwritten.
Consequently, a means for providing an interface between a host and a bus having multiple, high speed devices which can ensure coherency of data transfers is highly desirable.